1. Field of the Invention
The present invention relates to semiconductor devices and particularly to a semiconductor device including a shared sense amplifier.
2. Description of Related Art
Various semiconductor storage devices (which are referred to hereinafter as memories) are used in portable devices. Semiconductor devices used for portable devices need to operate with low power consumption so as to sustain a longer battery life of the portable device. Memories used for portable devices also need to operate with low power consumption. Further, there are increasing demands for large capacity and high-speed operation on memories, and the manufacturing process of memories is shifted to finer design rules to meet such demands. Furthermore, in order to provide larger capacity and higher-speed operation in circuits, a shared sense amplifier and a precharge circuit are used in a volatile memory such as a DRAM (Dynamic Random Access Memory).
A shared sense amplifier is used to provide larger capacity. In a DRAM, a shared sense amplifier is used for a cell array in which a plurality of memory cells are arranged in matrix to thereby reduce the number of sense amplifiers compared with a case where one sense amplifier is used for one cell array. With the shared sense amplifier, it is possible to read the data stored in a plurality of cell arrays using one sense amplifier. A switch circuit is disposed between the shared sense amplifier and each memory cell on the cell array with which the shared sense amplifier is connected, so that the shared sense amplifier can read the data of each memory cell one by one by controlling the switch circuit.
The precharge circuit is used to provide high-speed data processing. In a DRAM, the data of one memory cell is read using a pair of bit lines operating differentially with reference to a predetermined voltage to thereby detect a slight change in the bit line voltage and achieve high-speed data reading. Because the pair of bit lines operate in reference to a predetermined voltage, the two bit lines need to have the same voltage. To this end, such a memory typically includes a precharge circuit between a pair of bit lines. The precharge circuit operates when a memory is in the stand-by or non-selection state to supply a given voltage to each of the pair of bit lines so as to equalize their voltages.
However, as memories are manufactured according to finer design rules, the problem that element defect occurring during the manufacturing process causes an increase in leakage becomes significant. Particularly, if cross-fail occurs in a DRAM, leakage current increases to hinder the reduction of current in a memory cell in the non-selection state. The cross-fail is such that the drain and gate of a gate transistor of a memory cell are short-circuited with resistance. The cross-fail is difficult to detect in a shipping test because the drain and gate of a gate transistor are short-circuited with resistance and thus it functions as a transistor. A technique to reduce the current of a memory cell in the non-selection state when cross-fail occurs in a memory using a shared sense amplifier is disclosed in Japanese Unexamined Patent Publication No. 2005-243158.
FIG. 11 is a circuit diagram of a memory 100 of the related art disclosed in Japanese Unexamined Patent Publication No. 2005-243158. As shown in FIG. 11, the memory 100 of the related art includes a shared sense amplifier 101, switch circuits 102a and 102b, precharge circuits 103a and 103b, memory cells 104a and 104b, and word drivers 105a and 105b. In the memory 100 in the non-selection state, the switch circuits 102a and 102b are set to the conducting state (ON state), the bit lines BL and BLB are set to a precharge voltage HVDD (e.g. VDD/2) by the precharge circuits 103a and 103b, and the power supply voltage and the ground voltage of the shared sense amplifier are set to a non-selection voltage VDD/2. Further, a charge retention voltage VNN is supplied from the word drivers 105a and 105b to the gates of gate transistors N10a and N10b of the memory cells 104a and 104b, so that the gate transistors N10a and N10b are in the blocked state.
On the other hand, when reading the data stored in the memory cell 104a in the selection state, the switch circuit 102a is set to the ON state and the switch circuit 102b is set to the blocked state (OFF state) to thereby stop the operation of the precharge circuit 103a. Further, the power supply voltage and the ground voltage of the shared sense amplifier 101 are respectively set to a power supply voltage VDD and a ground voltage VSS. After that, a boosted voltage Vboot is supplied from the word driver 105a to the gate of the gate transistor N10a of the memory cell 104a. The charge of the bit line BL thereby changes according to the charge accumulated in a capacitor Ca. On the other hand, the charge of the bit line BLB does not change because nothing is connected with the bit line BLB. The shared sense amplifier amplifies a difference in charge between the bit line BL and the bit line BLB to thereby read the data stored in the memory cell 104a. 
When reading the data stored in the memory cell 104b in the selection state, the switch circuit 102a is set to the OFF state and the switch circuit 102b is set to the ON state to thereby stop the operation of the precharge circuit 103b. Further, the power supply voltage and the ground voltage of the shared sense amplifier 101 are respectively set to the power supply voltage VDD and the ground voltage VSS. After that, a boosted voltage Vboot is supplied from the word driver 105b to the gate of the gate transistor N10b of the memory cell 104b. The charge of the bit line BL thereby changes according to the charge accumulated in a capacitor Cb. On the other hand, the charge of the bit line BLB does not change because nothing is connected to the bit line BLB. The shared sense amplifier amplifies a difference in charge between the bit line BL and the bit line BLB to thereby read the data stored in the memory cell 104b. FIG. 12 collectively shows the conductive states of the switch circuits in these operations.
A case where cross-fail occurs in the memory 100 of the related art is described hereinafter. The following description is given on a case where cross-fail occurs in the gate transistor N10a of the memory cell 104a for example.
If cross-fail occurs in the gate transistor N10a, the drain and gate of the gate transistor are short-circuited with resistance. The bit line BL and the word line WL are thereby connected through resistance. As a result, leakage current flows according to a voltage difference between the precharge voltage HVDD and the charge retention voltage VNN. There are three paths for leakage current: a path from the precharge voltage HVDD of the precharge circuit 103a through transistors P3a and N7a to the bit line BL, a path from the non-selection voltage VDD/2 of the shared sense amplifier 101 through transistors P1 and N1 to the bit line BL, and a path from the precharge voltage HVDD of the precharge circuit 103b through transistors P3b and N7b to the bit line BL.
The memory 100 reduces the leakage current flowing through the precharge circuit by disposing a current limiter in the precharge circuit. The current limiters used in the memory 100 of FIG. 11 are the transistor P3a of the precharge circuit 103a and the transistor P3b of the precharge circuit 103b. The transistors P3a and P3b receive a constant voltage Vgate at their gates so as to have high resistance in the conducting state. The memory 100 of the related art can thereby reduce the leakage current by the transistors P3a and P3b. 
However, in the memory 100 of the related art, a current limiter is not placed between the shared sense amplifier 101 and the power supply. Accordingly, the leakage current flowing from the shared sense amplifier 101 upon occurrence of cross-fail is higher than the leakage current flowing from the precharge circuit. Further, because the shared sense amplifier 101 has large current consumption during the operation, the placement of a current limiter between the shared sense amplifier 101 and the power supply increases the power supply voltage drop to cause unstable operation.
Further, recent large capacity memories have a numerous number of memory cells and accordingly the number of places where cross-fail occur increases. In addition, the uses of a finer design rules for the manufacture of memories further increases the probability of the occurrence of cross-fails. Therefore, the leakage current of a chip as a whole cannot be reduced sufficiently merely with the use of a current limiter in a precharge circuit.